![]() You could add delays at the digital inputs using a similar circuit, or provide separate clocks which have dead-band built-in (an option on many MCUs with PWM motor control). Unfortunately this simple solution won't work properly in your design because the 35V Zener forces both Gate drives to have the same waveform, working against the Gate delay circuits. Simulate this circuit – Schematic created using CircuitLab The resistor combined with Gate capacitance increases charging time, while the diode allows it to discharge at (almost) normal speed. This can be done using a series resistor and paralleled diode in the Gate drive circuit. Shoot-through can be eliminated by adding a delay to the Gate turn-on so that one FET is fully off before the starts to turn on. This high current will quickly heat up the FETs and burn them out, perhaps violently if one of them becomes a dead short. During this time both FETs are partially on and Drain current (red) spikes up to 180-200A. Gate voltage (Blue, Green) changes relatively slowly due to the limited drive current available, particularly during the flat spot when Drain voltage is changing and Miller effect increases the apparent Gate capacitance. I simulated your circuit in LTspice, using FETs with similar Gate charge specs to yours. ![]() The result will be a large 'shoot-through' current during the transitions when both FETs are partially on. ![]() You don't have any dead-band, so one FET will be turning off while the other is turning on. ![]()
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